The present invention relates to a semiconductor memory device, and more particularly, to exemplary embodiments of a memory cell structure that can increase the separation spacing between closest adjacent memory elements for a given memory cell size.
A memory device normally comprises an array of memory cells, each of which includes a memory element and a selection transistor coupled in series between two electrodes. The selection transistor functions like a switch to direct current or voltage through the selected memory element coupled thereto. Upon application of an appropriate voltage or current to the memory element, the electrical property of the memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A memory device may be either volatile or non-volatile, depending on the types of memory element and memory architecture used. An example of volatile memory devices is dynamic random access memory (DRAM), which loses its stored information when power is interrupted or lost. Non-volatile memory devices, such as magnetic random access memory (MRAM) or other types of resistance-based memory devices, can retain stored information when powered off.
A resistance-based memory element can be classified into at least one of several known groups based on its resistance switching mechanism. The memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The memory element of Magnetic Random Access Memory (MRAM) typically comprises at least two layers of ferromagnetic materials with an insulating tunnel junction layer interposed therebetween. When a switching current is applied to the memory element of an MRAM device, one of the ferromagnetic layers will switch its magnetization direction with respect to that of the other magnetic layer, thereby changing the electrical resistance of the element.
FIG. 1 is a perspective view of a conventional memory device 20 comprising a semiconductor substrate 30, a plurality of memory cells 32 formed thereon, a plurality of parallel gates 34 connecting to the cells 32 along the y-direction, a plurality of parallel common source lines 36 connecting the cells 32 along the y-direction, and a plurality of bit lines 38 connecting the cells 32 along the x-direction substantially perpendicular to the y-direction. In this drawing, the insulation material separating various elements is omitted for reasons of clarity. Each of the memory cells 32 further includes a resistance-based memory element 40 and a selection transistor 42 connected in series by way of a bit contact 44. Each selection transistor 42 includes a drain and a common source that is shared with an adjacent selection transistor. The bit contact 44 is formed on top of the drain. Each common source is coupled to one of the common source lines 36 formed thereon. The channel of the selection transistor 42 formed between the drain and the common source beneath the gate 34 has a length of about 1 F and a width of about 1 F, where F denotes the minimum feature size or one half the minimum feature pitch normally associated with a particular lithography process. In memory applications where memory cells are arranged in dense and repetitive patterns, photolithography is more constrained by the pitch of the feature pattern rather than the feature size itself. This is because the feature size can be modulated by photo lithography process conditions, such as exposure and resist development, but shrinkage of the feature pitch would require shorter wavelength light source and/or significant improvement in optics. In reality, the scaling of the device size in a dense array, such as that in memory applications, is limited by the minimum pitch of 2 F. Moreover, it is normally assumed that the minimum feature size is half of the corresponding minimum pitch. The illustrated conventional resistive memory device in FIG. 1 has cell dimensions of 4 F and 2 F in the directions of the bit lines 38 and the source lines 36, respectively, resulting in a cell size of 8 F2.
FIG. 2 is a top planar view of the conventional memory device 20 showing the placement of the gates 34, the common source lines 36, the memory elements 40, and the bit contacts 44 directly beneath the memory elements 40. For reasons of clarity, the bit lines 38 are not shown in order to expose the structure therebeneath. The center-to-center spacing between any one of the bit contacts 44 and the three closest neighbors thereof is 2 F. The memory elements 40, which are formed on top of the bit contacts 44, are subjected to the same geometric constraint with the center-to-center spacing between two closest neighbors being 2 F. Assuming each of the memory elements 40 has a diameter of about 1 F, then the gap or clearance between two closest adjacent memory elements 40 is only about 1 F. For 8 F2 memory cell design, such as the one shown in FIGS. 1 and 2, it is desirable to increase the spacing or separation between two closest adjacent memory elements 40 in order to increase the gap therebetween for easing processing constraints or to increase the memory size for improving memory performance or both.
For the foregoing reasons, there is a need for an 8 F2 memory device that has a minimum center-to-center spacing between adjacent memory elements greater than 2 F and that can be inexpensively manufactured.